View CS5346-CQZR_7020930.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

copyright ? cirrus logic, inc. 2010 (all rights reserved) http://www.cirrus.com preliminary product information this document contains information for a product under development. cirrus logic reserves the right to modify this produ ct without notice. 103-db, 192-khz, stereo audio adc with 6:1 input mux adc features ? multi-bit delta sigma modulator ? 103 db dynamic range ? -95 db thd+n ? stereo 6:1 input multiplexer ? programmable gain amplifier (pga) ? 12 db gain, 0.5-db step size ? zero-crossing, click-free transitions ? stereo microphone inputs ? +32 db gain stage ? low-noise bias supply ? up to 192 khz sampling rates ? selectable 24-bit, left-justified or i2s serial audio interface formats system features ? power-down mode ? +5 v analog power supply, nominal ? +3.3 v digital power supply, nominal ? direct interface with 3.3 v to 5 v logic levels ? pin compatible with cs5345 (*see section 2 for details.) general description the cs5346 integrates an analog multiplexer, program- mable gain amplifier, and stereo audio analog-to-digital converter. the cs5346 perfor ms stereo analog-to-digi- tal (a/d) conversion of 24-bit serial values at sample rates up to 192 khz. a 6:1 stereo input multiplexe r is included for selecting between line-level and microphone-level inputs. the microphone input path includes a +32 db gain stage and a low-noise bias voltage supply. the pga is avail- able for line or microphone inputs and provides gain/attenuation of 12 db in 0.5 db steps. the output of the pga is followed by an advanced 5th- order, multi-bit delta-sigma modulator and digital filter- ing/decimation. sampled data is transmitted by the serial audio interface at rates from 8 khz to 192 khz in either slave or master mode. integrated level translators allow easy interfacing be- tween the cs5346 and other devices operating over a wide range of logic levels. the cs5346 is available in a 48-pin lqfp package in commercial (-40 to +85 c) and automotive (-40 to +105 c) grades. the cdb5346 customer demonstra- tion board is also available for device evaluation and implementation suggestions. please refer to ?ordering information? on page 40 for complete details. 3.3 v to 5 v low-latency anti-alias filter internal voltage reference multibit oversampling adc multibit oversampling adc low-latency anti-alias filter high pass filter high pass filter stereo input 1 serial audio output 3.3 v 5 v mux pcm serial interface register configuration level translator stereo input 2 stereo input 3 stereo input 4 / mic input 1 & 2 stereo input 5 stereo input 6 pga +32 db +32 db level translator reset i2c ? /spi ? control data interrupt overflow left pga output right pga output pga september ?10 ds861pp2 cs5346
2 ds861pp2 cs5346 table of contents 1. pin descriptions - cs5346 ................................................................................................. ............ 5 2. pin compatibility - cs5345/cs5346 differenc es ..................................................................... 7 3. characteristics and specificat ions .......... ................. ................ ................ ................ ........... 8 recommended operating conditions ................................................................................... 8 absolute maximum ratings ...................................................................................................... .8 analog characteristics (commercial) ................................................................................ 9 analog characteristics (commercial) cont. .................................................................. 10 analog characteristics (automotive) ............................................................................... 11 analog characteristics (automotive) cont. ... ................................................................ 12 digital filter characteristics .............................................................................................. 13 dc electrical characteristics ............................................................................................. 14 digital interface characteristics ...................................................................................... 15 switching characteristics - serial audio port ............................................................. 16 switching characteristics - control port - i2c format ............................................ 18 switching characteristics - control port - spi format ........................................... 19 4. typical connection diagram ................................................................................................. .. 20 5. applications ............................................................................................................... .................... 21 5.1 recommended power-up sequence ............................................................................................. 21 5.2 system clocking ........................................................................................................... .................. 21 5.2.1 master clock ............................................................................................................ ............. 21 5.2.2 master mode ............................................................................................................. ............ 22 5.2.3 slave mode .............................................................................................................. ............. 22 5.3 high-pass filter and dc offset calibration ................................................................................ .... 22 5.4 analog input multiplexer, pga, and mic gain ............................................................................... .23 5.5 input connections ......................................................................................................... .................. 23 5.5.1 analog input configuration for 1 vrms input levels ............................................................ 23 5.5.2 analog input configuration for 2 vrms input levels ............................................................ 24 5.6 pga auxiliary analog output ............................................................................................... .......... 25 5.7 control port description and timing ....................................................................................... ........ 25 5.7.1 spi mode ................................................................................................................ ............... 25 5.7.2 i2c mode ................................................................................................................ ................ 26 5.8 interrupts and overflow ................................................................................................... ............... 27 5.9 reset ..................................................................................................................... ......................... 28 5.10 synchronization of multiple devices ...................................................................................... ....... 28 5.11 grounding and power supply decoupling .................................................................................... 28 6. register quick reference ................................................................................................... ..... 29 7. register description ....................................................................................................... ........... 30 7.1 chip id - register 01h .................................................................................................... ................ 30 7.2 power control - address 02h ...................... ......................................................................... .......... 30 7.2.1 freeze (bit 7) .......................................................................................................... ............... 30 7.2.2 power-down mic (bit 3) .................................................................................................. ...... 30 7.2.3 power-down adc (bit 2) .................................................................................................. ..... 30 7.2.4 power-down device (bit 0) ............................................................................................... .... 30 7.3 adc control - address 04h ................................................................................................. ........... 31 7.3.1 functional mode (bits 7:6) .............................................................................................. ...... 31 7.3.2 digital interface format (b it 4) ........................................................................................ ...... 31 7.3.3 mute (bit 2) ............................................................................................................ ................ 31 7.3.4 high-pass filter freeze (b it 1) ......................................................................................... ..... 31 7.3.5 master / slave mode (bit 0) ............................................................................................. ...... 31 7.4 mclk frequency - address 05h .............................................................................................. ...... 32 7.4.1 master clock dividers (bits 6:4) ........................................................................................ .... 32 7.5 pgaout control - address 06h .............................................................................................. ........ 32
ds861pp2 3 cs5346 7.5.1 pgaout source select (bit 6) ............................................................................................ ... 32 7.6 channel b pga control - address 07h ....................................................................................... ... 32 7.6.1 channel b pga gain (bits 5:0) ........................................................................................... .. 32 7.7 channel a pga control - address 08h ....................................................................................... ... 33 7.7.1 channel a pga gain (bits 5:0) ........................................................................................... .. 33 7.8 adc input control - address 09h ........................................................................................... ........ 33 7.8.1 pga soft ramp or zero cross enable (bits 4:3) .................................................................. 33 7.8.2 analog input selection (bits 2:0) ....................................................................................... .... 34 7.9 active level control - address 0ch ........................................................................................ ........ 34 7.9.1 active high/ low (bit 0) ................................................................................................ ......... 34 7.10 status - address 0dh ..................................................................................................... .............. 34 7.10.1 clock error (bit 3) .................................................................................................... ............ 35 7.10.2 overflow (bit 1) ....................................................................................................... ............. 35 7.10.3 underflow (bit 0) ...................................................................................................... ............ 35 7.11 status mask - address 0eh ................................................................................................ .......... 35 7.12 status mode msb - address 0fh ................. ........................................................................... ..... 35 7.13 status mode lsb - address 10h ............... ............................................................................. ...... 35 8. parameter definitions ...................................................................................................... .......... 36 9. filter plots ............................................................................................................... ...................... 37 10. package dimensions ........................................................................................................ .......... 39 11. thermal characteristics and specifications .............................................................. 39 12. ordering information ...................................................................................................... ........ 40 13. revision history .......................................................................................................... ................ 40 list of figures figure 1.master mode serial audio port timing ................................................................................. ...... 17 figure 2.slave mode serial audio port timing .................................................................................. ....... 17 figure 3.format 0, 24-bit data left-justified ................................................................................. ........... 17 figure 4.format 1, 24-bit data i2s ............................................................................................ ................ 17 figure 5.control port timing - i2c format ....... .............................................................................. ............ 18 figure 6.control port timing - spi format ..................................................................................... ........... 19 figure 7.typical connection diagram .................... ....................................................................... ............ 20 figure 8.master mode clocking ................................................................................................. ............... 22 figure 9.analog input architecture ............................................................................................ ................ 23 figure 10.cs5346 pga .......................................................................................................... .................. 24 figure 11.1 v rms input circuit ................................................................................................................ .. 24 figure 12.1 v rms input circuit with rf filtering .................... ................................................................... 24 figure 13.2 v rms input circuit ................................................................................................................ .. 24 figure 14.control port timing in spi mode ..................................................................................... ......... 26 figure 15.control port timing, i2c write ...................................................................................... ............. 26 figure 16.control port timing, i2c read ....................................................................................... ............ 27 figure 17.single- speed stopband rejection ..................................................................................... ....... 37 figure 18.single- speed stopband rejection ..................................................................................... ....... 37 figure 19.singl e-speed transition band (detail) ............................................................................... ....... 37 figure 20.single-speed passband ripple ........................................................................................ ........ 37 figure 21.double-speed st opband rejection ..................................................................................... ...... 37 figure 22.double-speed st opband rejection ..................................................................................... ...... 37 figure 23.double-speed transition band (detail) ............................................................................... ..... 38 figure 24.double-speed passband ripple ............... ......................................................................... ....... 38 figure 25.quad-speed stopband rejection ....................................................................................... ...... 38 figure 26.quad-speed stopband rejection ....................................................................................... ...... 38 figure 27.quad-s peed transition band (det ail) ................................................................................. ...... 38 figure 28.quad-sp eed passband ripple .......................................................................................... ....... 38
4 ds861pp2 cs5346 list of tables table 1. speed modes .......................................................................................................... .................... 21 table 2. common clock frequencies ............................................................................................. .......... 21 table 3. slave mode serial bit clock ratios ... ................................................................................ .......... 22 table 4. device revision ...................................................................................................... .................... 30 table 5. freeze-able bits ..................................................................................................... ..................... 30 table 6. functional mode sele ction ............................................................................................ .............. 31 table 7. digital interface formats ............................................................................................ ................. 31 table 8. mclk frequency ....................................................................................................... ................. 32 table 9. pgaout source select ion .............................................................................................. ............. 32 table 10. example gain and attenuation settings ............................................................................... .... 33 table 11. pga soft cross or zero cross mode select ion ........................................................................ 3 4 table 12. analog input multiplexe r selection .................................................................................. .......... 34
ds861pp2 5 cs5346 1. pin descriptions - cs5346 pin name # pin description sda/cdout 1 serial control data ( input / output ) - sda is a data i/o in i2c ? mode. cdout is the output data line for the control port interface in spi tm mode. scl/cclk 2 serial control port clock ( input ) - serial clock for th e serial control port. ad0/cs 3 address bit 0 (i2c) / control port chip select (spi) (input) - ad0 is a chip address pin in i2c mode; cs is the chip-select signal for spi format. ad1/cdin 4 address bit 1 (i2c) / serial control data input (spi) (input) - ad1 is a chip address pin in i2c mode; cdin is the input data line for the c ontrol port interface in spi mode. vlc 5 control port power ( input ) - determines the required signal level fo r the control port interface. refer to the recommended operating conditions for appropriate voltages. rst 6 reset ( input ) - the device enters a low-power mode when this pin is driven low. ain3a ain3b 7 8 stereo analog input 3 ( input ) - the full-scale level is specified in the analog characteristics specifica- tion table. ain2a ain2b 9 10 stereo analog input 2 ( input ) - the full-scale level is specified in the analog characteristics specifica- tion table. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vls sda/cdout agnd ovfl scl/cclk ad0/cs ad1/cdin vlc rst ain3a ain3b ain2a ain2b ain1a ain1b va afiltb vq vq filt+ nc ain4a/micin1 ain4b/micin2 ain5a ain5b afilta nc nc nc agnd nc nc pgaoutb pgaouta ain6b ain6a micbias int vd dgnd mclk lrck sclk sdout nc nc nc nc cs5346
6 ds861pp2 cs5346 ain1a ain1b 11 12 stereo analog input 1 ( input ) - the full-scale level is specified in the analog characteristics specifica- tion table. agnd 13 analog ground ( input ) - ground reference for the internal analog section. va 14 analog power (input) - positive power for the internal analog section. afilta 15 anti-alias filt er connection ( output ) - antialias filter connection for the channel a adc input. afiltb 16 anti-alias filt er connection ( output ) - antialias filter connection for the channel b adc input. vq 17 18 quiescent voltage ( output ) - filter connection for the internal quiescent reference voltage. filt+ 19 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. nc 20 no connect - this pin is not connected internally and should be tied to ground to minimize any poten- tial coupling effects. ain4a/micin1 ain4b/micin2 21 22 stereo analog input 4 / microphone input 1 & 2 ( input ) - the full-scale level is specified in the ana- log characteristics specification table. ain5a ain5b 23 24 stereo analog input 5 ( input ) - the full-scale level is specified in the analog characteristics specifica- tion table. micbias 25 microphone bias supply ( output ) - low-noise bias supply for external microphone. electrical charac- teristics are specified in the dc electrical characteristics specification table. ain6a ain6b 26 27 stereo analog input 6 ( input ) - the full-scale level is specified in the analog characteristics specifica- tion table. pgaouta pgaoutb 28 29 pga analog audio output ( output ) - either an analog output from the pga block or high impedance. see ?pgaout source select (bit 6)? on page 32 . nc 30 31 no connect - these pins are not connected internally a nd should be tied to ground to minimize any potential coupling effects. agnd 32 analog ground ( input ) - ground reference for the internal analog section. nc 33 34 35 no connect - these pins are not connected internally a nd should be tied to ground to minimize any potential coupling effects. vls 36 serial audio interface power ( input ) - determines the required signal level for the serial audio inter- face. refer to the recommended operating conditions for appropriate voltages. nc 37 38 39 40 no connect - these pins are not connected internally a nd should be tied to ground to minimize any potential coupling effects. sdout 41 serial audio data output ( output ) - output for two?s complement serial audio data. sclk 42 serial clock (input/output ) - serial clock for the serial audio interface. lrck 43 left right clock (input/output ) - determines which channel, left or right, is currently active on the serial audio data line. mclk 44 master clock ( input ) - clock source for the adc? s delta-sigma modulators. dgnd 45 digital ground ( input ) - ground reference for the internal digital section. vd 46 digital power ( input ) - positive power for the internal digital section. int 47 interrupt ( output ) - indicates an interrupt condition has occurred. ovfl 48 overflow ( output ) - indicates an adc overflow condition is present.
ds861pp2 7 cs5346 2. pin compatibility - cs 5345/cs5346 differences the cs5346 is pin compatible with the cs5345 and is a drop in replacement for cs5345 applications where va = 5 v, vd = 3.3 v, vls ? 3.3 v, and vlc ? 3.3 v. the pinout diagram and table below show the requirements for the remaining pins when replacing the cs5345 in these designs with a cs5346. # cs5345 pin name cs5346 pin name cs5346 connection for compatibility 5vlc vlc control port power ( input ) -limited to nominal 5 or 3.3 v. 14 va va analog power (input) - limited to nominal 5 v. 18 tsto vq this pin must be left unconnected. 20 tsti nc this pin should be tied to ground. 30 va nc this pin may be connected to the analog supply voltage. the decoupling capacitor for the cs5345 is not required. 31 agnd nc this pin should be connected to ground. 35 tsto nc this pin may be left unconnected. 36 vls vls serial audio interface power ( input ) - limited to nominal 5 or 3.3 v. 37 tsti nc this pin should be tied to ground. 46 vd vd digital power ( input ) - limited to nominal 3.3 v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vls sda/cdout agnd ovfl scl/cclk ad0/cs ad1/cdin vlc rst ain3a ain3b ain2a ain2b ain1a ain1b va afiltb vq tsto filt+ tsti ain4a/micin1 ain4b/micin2 ain5a ain5b afilta tsto nc nc agnd agnd va pgaoutb pgaouta ain6b ain6a micbias int vd dgnd mclk lrck sclk sdout nc nc nc tsti cs5345 compatibility
8 ds861pp2 cs5346 3. characteristics and specifications recommended operating conditions agnd = dgnd = 0 v; all voltages with respect to ground. absolute maximum ratings agnd = dgnd = 0 v all voltages with respect to ground. (note 1) notes: 1. operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. 2. any pin except supplies. transient currents of up to 100 ma on the analog input pins will not cause scr latch-up. parameters symbol min nom max units dc power supplies: analog digital logic - serial port logic - control port va vd vls vlc 4.75 3.13 3.13 3.13 5.0 3.3 3.3 3.3 5.25 3.47 5.25 5.25 v v v v ambient operating temperature (power applied) commercial automotive t a t a -40 -40 - - +85 +105 ? c ? c parameter symbol min max units dc power supplies: analog digital logic - serial port logic - control port va vd vls vlc -0.3 -0.3 -0.3 -0.3 +6.0 +3.63 +6.0 +6.0 v v v v input current (note 2) i in - ? 10 ma analog input voltage v ina agnd-0.3 va+0.3 v digital input voltage logic - serial port logic - control port v ind-s v ind-c -0.3 -0.3 vls+0.3 vlc+0.3 v v ambient operating temperature (power applied) t a -50 +125 ? c storage temperature t stg -65 +150 ? c
ds861pp2 9 cs5346 analog characteristi cs (commercial) test conditions (unless otherwise specified): va = 5 v; vd = vls = vlc = 3.3 v; agnd = dgnd = 0 v; t a = +25 c; input test signal: 1 khz sine wave; measurement bandwidth is 10 hz to 20 khz; fs = 48/96/192 khz; pga gain = 0 db; all connections as shown in figure 7 on page 20 . 3. valid for double- and quad-speed modes only. 4. referred to the typical a/d full-scale input voltage 5. valid when the microphone-level inputs are selected. parameter symbol min typ max unit analog-to-digital converter characteristics dynamic range (line level inputs) a-weighted unweighted (note 3) 40 khz bandwidth unweighted 97 94 - 103 100 98 - - - db db db total harmonic distortion + noise (line level inputs) (note 4) -1 db -20 db -60 db (note 3) 40 khz bandwidth -1 db thd+n - - - - -95 -80 -40 -92 -89 - - - db db db db dynamic range (mic level inputs) a-weighted (note 3) unweighted 77 74 83 80 - - db db total harmonic distortion + noise (mic level inputs) (note 4) -1 db -20 db (note 3) -60 db thd+n - - - -80 -60 -20 -74 - - db db db interchannel isolation (line level inputs) (mic level inputs) - - 90 80 - - db db a/d full-scale input voltage 0.51*va 0.57*va 0.63*va v pp gain error -- ? 10 % interchannel gain mismatch - 0.1 - db microphone - level input characteristics preamplifier gain 31 35.5 32 40 33 44.7 db v/v interchannel gain mismatch - 0.1 - db input impedance (note 5) -60-k ?
10 ds861pp2 cs5346 analog characterist ics (commercial) cont. 6. referred to the typical a/d full-scale input voltage. parameter symbol min typ max unit line-level input and programmable gain amplifier gain range - 12 -4 - - + 12 +4 db v/v gain step size -0.5-db absolute gain step error - - 0.4 db maximum input level - - 0.85*va v pp input impedance selected inputs un-selected inputs 28.8 - 36 - 43.2 38 k ? k ? selected interchannel input impedance mismatch - 5 - % analog outputs dynamic range (line level inputs) a-weighted unweighted 98 95 104 101 - - db db total harmonic distortion + noise (line level inputs) (note 6) -1 db -20 db -60 db thd+n - - - -80 -81 -41 -74 - - db db db dynamic range (mic level inputs) a-weighted unweighted 77 74 83 80 - - db db total harmonic distortion + noise (mic level inputs) (note 6) -1 db -20 db -60 db thd+n - - - -74 -60 -20 -68 - - db db db frequency response 10 hz to 20 khz -0.1db - +0.1db db analog in to analog out phase shift - 180 - deg dc current draw from a pgaout pin i out --1 ? a ac-load resistance r l 100 - - k ? load capacitance c l --20pf
ds861pp2 11 cs5346 analog characteristics (automotive) test conditions (unless otherwise specified): va = 5.0 v +/- 5%; vd = vls = vlc = 3.3 v +/- 5%; agnd = dgnd = 0 v; t a = -40 to +85 c; input test signal: 1 khz si ne wave; measurement ba ndwidth is 10 hz to 20 khz; fs = 48/96/192 khz; pga gain = 0 db; all connections as shown in figure 7 on page 20 . 7. valid for double- and quad-speed modes only. 8. referred to the typical a/d full-scale input voltage 9. valid when the microphone-level inputs are selected. parameter symbol min typ max unit analog-to-digital converter characteristics dynamic range (line level inputs) a-weighted unweighted (note 3) 40 khz bandwidth unweighted 95 92 - 103 100 98 - - - db db db total harmonic distortion + noise (line level inputs) (note 4) -1 db -20 db -60 db (note 3) 40 khz bandwidth -1 db thd+n - - - - -95 -80 -40 -92 -87 - - - db db db db dynamic range (mic level inputs) a-weighted (note 3) unweighted 75 72 83 80 - - db db total harmonic distortion + noise (mic level inputs) (note 4) -1 db -20 db (note 3) -60 db thd+n - - - -80 -60 -20 -72 - - db db db interchannel isolation (line level inputs) (mic level inputs) - - 90 80 - - db db a/d full-scale input voltage 0.51*va 0.57*va 0.63*va v pp gain error -- ? 10 % interchannel gain mismatch - 0.1 - db microphone - level input characteristics preamplifier gain 31 35.48 32 40 33 44.67 db v/v interchannel gain mismatch - 0.1 - db input impedance (note 5) -60-k ?
12 ds861pp2 cs5346 analog characterist ics (automotive) cont. 10. referred to the typical a/d full-scale input voltage. parameter symbol min typ max unit line-level input and programmable gain amplifier gain range - 12 -4 - - + 12 +4 db v/v gain step size -0.5-db absolute gain step error - - 0.4 db maximum input level - - 0.85*va v pp input impedance selected inputs un-selected inputs 28.8 - 36 - 43.2 38 k ? k ? selected interchannel input impedance mismatch - 5 - % analog outputs dynamic range (line level inputs) a-weighted unweighted 96 93 104 101 - - db db total harmonic distortion + noise (line level inputs) (note 6) -1 db -20 db -60 db thd+n - - - -80 -81 -41 -74 - - db db db dynamic range (mic level inputs) a-weighted unweighted 77 74 83 80 - - db db total harmonic distortion + noise (mic level inputs) (note 6) -1 db -20 db -60 db thd+n - - - -74 -60 -20 -68 - - db db db frequency response 10 hz to 20 khz -0.1db - +0.1db db analog in to analog out phase shift - 180 - deg dc current draw from a pgaout pin i out --1 ? a ac-load resistance r l 100 - - k ? load capacitance c l --20pf
ds861pp2 13 cs5346 digital filter characteristics 11. response is clock-dependent and will scale wi th fs. note that the response plots ( figures 17 to 28 ) are normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. 12. response shown is for fs = 48 khz. parameter (note 11 ) symbol min typ max unit single-speed mode passband (-0.1 db) 0 - 0.4896 fs passband ripple - - 0.035 db stopband 0.5688 - - fs stopband attenuation 70 - - db total group delay (fs = output sample rate) t gd -12/fs - s double-speed mode passband (-0.1 db) 0 - 0.4896 fs passband ripple - - 0.025 db stopband 0.5604 - - fs stopband attenuation 69 - - db total group delay (fs = output sample rate) t gd -9/fs - s quad-speed mode passband (-0.1 db) 0 - 0.2604 fs passband ripple - - 0.025 db stopband 0.5000 - - fs stopband attenuation 60 - - db total group delay (fs = output sample rate) t gd -5/fs - s high-pass filter characteristics frequency response -3.0 db -0.13 db (note 12) -1 20 - - hz hz phase deviation @ 20 hz (note 12) -10 -deg passband ripple -- 0db filter settling time 10 5 /fs s
14 ds861pp2 cs5346 dc electrical characteristics agnd = dgnd = 0 v, all voltages with respect to gr ound. mclk=12.288 mhz; fs =48 khz; master mode. 13. power-down mode is defines as rst = low with all clock and data lines held static and no analog input. 14. valid with the recommended capacitor values on filt+ and vq as shown in the typical connection diagram. parameter symbol min typ max unit power supply current va = 5 v (normal operation) vd, vls, vlc = 3.3 v i a i d - - 41 23 50 28 ma ma power supply current va = 5 v (power-down mode) (note 13) vls, vlc, vd = 3.3 v i a i d - - 0.50 0.54 - - ma ma power consumption (normal operation) va = 5 v vd, vls, vlc = 3.3 v (power-down mode) va = 5v; vd, vls, vlc = 3.3 v - - - - - - 205 76 4.2 250 93 - mw mw mw power supply rejection ratio (1 khz) (note 14) psrr - 55 - db vq characteristics quiescent voltage vq - 0.5 x va - vdc maximum dc current from vq i q -1 - ? a vq output impedance z q -23 -k ? filt+ nominal voltage filt+ - va - vdc microphone bias voltage micbias - 0.8 x va - vdc current from micbias i mb -- 2ma
ds861pp2 15 cs5346 digital interface characteristics test conditions (unless otherwise specifie d): agnd = dgnd = 0 v; vls = vlc = 3.3 v. 15. serial port signals include: mclk, sclk, lrck, sdout. control port signal s include: scl/cclk, sda/cdout, ad0/cs , ad1/cdin, rst , int, ovfl. parameters (note 15) symbol min typ max units high-level input voltage serial port control port v ih v ih 0.7xvls 0.7xvlc - - - - v v low-level input voltage serial port control port v il v il - - - - 0.3xvls 0.3xvlc v v high-level output voltage at i o = 2 ma serial port control port v oh v oh vls-1.0 vlc-1.0 - - - - v v low-level output voltage at i o = 2 ma serial port control port v ol v ol - - - - 0.4 0.4 v v input leakage current i in --10 ? a input capacitance - 1 - pf minimum ovfl active time - - ? s 10 6 lrck ---------------- -
16 ds861pp2 cs5346 switching characteristic s - serial audio port logic ?0? = dgnd = agnd = 0 v; logic ?1? = vls, c l = 20 pf. (note 16) 16. see figure 1 and figure 2 on page 17 . parameter symbol min typ max unit sample rate single-speed mode double-speed mode quad-speed mode fs fs fs 8 50 100 - - - 50 100 200 khz khz khz mclk specifications mclk frequency f mclk 2.048 - 51.200 mhz mclk input pulse width high/low t clkhl 8- -ns master mode lrck duty cycle - 50 - % sclk duty cycle - 50 - % sclk falling to lrck edge t slr -10 - 10 ns sclk falling to sdout valid t sdo 0-36ns slave mode lrck duty cycle 40 50 60 % sclk period single-speed mode double-speed mode quad-speed mode t sclkw t sclkw t sclkw - - - - - - ns ns ns sclk pulse width high t sclkh 30 - - ns sclk pulse width low t sclkl 48 - - ns sclk falling to lrck edge t slr -10 - 10 ns sclk falling to sdout valid t sdo 0-36ns 10 9 128 ?? fs -------------------- - 10 9 64 ?? fs ----------------- - 10 9 64 ?? fs ----------------- -
ds861pp2 17 cs5346 slr t sdout sclk output lrck output sdo t slr t sdout sclk input lrck input sdo t sclkh t sclkl t sclkw t figure 1. master mode serial audio port timing figure 2. slave mode serial audio port timing figure 3. format 0, 24-bit data left-justified lrck sclk sdata +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 msb -1 -2 -3 -4 channel a - left channel b - right lsb lsb msb figure 4. format 1, 24-bit data i2s lrck sclk sdata +3 +2 +1 +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 channel a - left channel b - right lsb msb lsb
18 ds861pp2 cs5346 switching characteristics - control port - i2c format inputs: logic 0 = dgnd = agnd = 0 v, logic 1 = vlc, c l =30pf. 17. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 17) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc , t rd -1s fall time scl and sda t fc , t fd - 300 ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst figure 5. control po rt timing - i2c format
ds861pp2 19 cs5346 switching characteristics - control port - spi format inputs: logic 0 = dgnd = agnd = 0 v, logic 1 = vlc, c l =30pf. 18. data must be held for sufficient time to bridge the transition time of cclk. 19. for f sck <1 mhz. parameter symbol min max units cclk clock frequency f sck -6.0mhz rst rising edge to cs falling t srs 500 - ns cs high time between transmissions t csh 1.0 - ? s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 18) t dh 15 - ns cclk falling to cdout stable t pd -50ns rise time of cdout t r1 -25ns fall time of cdout t f1 -25ns rise time of cclk and cdin (note 19) t r2 - 100 ns fall time of cclk and cdin (note 19) t f2 - 100 ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t pd cdout t csh rst t srs figure 6. control po rt timing - spi format
20 ds861pp2 cs5346 4. typical connection diagram vls 0.1 f +3.3v to +5v dgnd vlc 0.1 f +3.3v to +5v scl/cclk sda/cdout ad1/cdin rst 2 k ? see note 1 ad0/cs note 1: resistors are required for i2c control port operation micro- controller digital audio capture lrck sdout mclk sclk pgaouta pgaoutb 2.2nf afilta afiltb ovfl 2.2nf 3.3 f 3.3 f 47 f 0.1 f vq filt+ 10 f agnd 2 k ? int 47 f ain1a left analog input 1 ain1b right analog input 1 ain2a left analog input 2 ain2b right analog input 2 ain3a left analog input 3 ain3b right analog input 3 ain4a/micin1 left analog input 4 ain4b/micin2 right analog input 4 ain5a left analog input 5 ain5b right analog input 5 ain6a left analog input 6 ain6b right analog input 6 micbias agnd 0.1 f nc nc nc nc nc nc nc nc nc 10 f +3.3v 0.1 f 10 f 0.1 f va vd +5v r l see note 2 note 2 the value of r l is dictated by the microphone carteridge. cs5346 analog input 3 analog input 3 analog input 3 analog input 3 analog input 3 analog input 3 analog input 3 analog input 3 analog input 3 analog input 3 analog input 3 analog input 3 vq note 3: see section 5.5.1. afilta and afiltb capacitors must be c0g or equivalent figure 7. typical connection diagram note 3. see section 5.5.1 .
ds861pp2 21 cs5346 5. applications 5.1 recommended power-up sequence 1. hold rst low until the power supply, mclk, and lrck are st able. in this state, th e control port is reset to its default settings. 2. bring rst high. the device will remain in a low power state wit h the pdn bit set by default. the control port will be accessible. 3. the desired register settings can be loaded while the pdn bit remains set. 4. clear the pdn bit to initiate the power-up sequence. 5.2 system clocking the cs5346 will operate at sa mpling frequencies from 8 k hz to 200 khz. this range is divided into three speed modes as shown in table 1 . 5.2.1 master clock mclk/lrck must maintain an integer ratio as shown in table 2 . the lrck frequency is equal to fs, the frequency at which audio samples for each channel are clocked out of the device. the fm bits (see ?func- tional mode (bits 7:6)? on page 31. ) and the mclk freq bits (see ?mclk frequency - address 05h? on page 32. ) configure the device to generate the proper clocks in master mode and receive the proper clocks in slave mode. table 2 illustrates several standa rd audio sample rates an d the required mclk and lrck frequencies. mode sampling frequency single-speed 8-50 khz double-speed 50-100 khz quad-speed 100-200 khz table 1. speed modes lrck (khz) mclk (mhz) * 64x * 96x 128x 192x 256x 384x 512x 768x 1024x 32 - --- 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 - --- 11.2896 16.9344 22.5792 33.8680 45.1584 48 - --- 12.2880 18.4320 24.5760 36.8640 49.1520 64 - - 8.1920 12.2880 16.3840 24.5760 32.7680 - - 88.2 - - 11.2896 16.9344 22.5792 33.8680 45.1584 - - 96 - - 12.2880 18.4320 24.5760 36.8640 49.1520 - - 128 8.1920 12.2880 16.3840 24.5760 32.7680 - - - - 176.4 11.2896 16.9344 22.5792 33.8680 45.1584 - - - - 192 12.2880 18.4320 24.5760 36.8640 49.1520 - - - - mode qsm dsm ssm * only available in master mode. table 2. common clock frequencies
22 ds861pp2 cs5346 5.2.2 master mode as a clock master, lrck and sclk will operate as out puts. lrck and sclk are internally derived from mclk with lrck equal to fs and sclk equal to 64 x fs as shown in figure 8 . 5.2.3 slave mode in slave mode, sclk and lrck operate as inputs. the left/right clock signal must be equal to the sam- ple rate, fs, and must be synchronously derived from the supplied master clock, mclk. the serial bit clock, sclk, must be synchronously de rived from the master clock, mclk, and be equal to 128x, 64x or 48x fs, depending on the desired speed mode. refer to table 3 for required clock ratios. 5.3 high-pass filter a nd dc offset calibration when using operational amplifiers in the input circui try driving the cs5346, a small dc offset may be driven into the a/d converter. the cs5346 includes a high-pa ss filter after the decimator to remove any dc offset which could result in recording a dc level, possibly yielding clicks when switching between devices in a mul- tichannel system. the high-pass filter continuously s ubtracts a measure of t he dc offset from the ou tput of the decimation filter. if the hpffreeze bit (see ?high-pass filter freeze (bit 1)? on page 31. ) is set during normal operation, the current value of the dc offset for the each channel is froz en and this dc offset will continue to be sub- tracted from the conversion result. this feature makes it possible to perform a system dc offset calibration by: 1. running the cs5346 with the high-pass filter enabled un til the filter settles. se e the digital filter char- acteristics section for filter settling time. 2. disabling the high-pass filter an d freezing the stored dc offset. a system calibration performed in th is way will eliminate offsets anywhere in the signal path between the calibration point and the cs5346. single-speed double-speed quad-speed sclk/lrck ratio 48x, 64x, 128x 48x, 64x 48x, 64x table 3. slave mode serial bit clock ratios 256 128 64 4 2 1 00 01 10 00 01 10 lrck sclk 000 001 010 1 1.5 2 011 100 3 4 mclk fm bits mclk freq bits figure 8. master mode clocking
ds861pp2 23 cs5346 5.4 analog input multipl exer, pga, and mic gain the cs5346 contains a stereo 6-to-1 analog input multiplexer followed by a programmable gain amplifier (pga). the input multiplexer can select one of six poss ible stereo analog input sources and route it to the pga. analog inputs 4a and 4b are able to insert a +3 2 db (+40x) gain stage before the input multiplexer, allowing them to be used for microphone-level sign als without the need for any external gain. the pga stage provides ? 12 db ( ? 4x) adjustment in 0.5 db steps. figure 9 shows the architecture of the input multi- plexer, pga, and microphone gain stages. the ? ?analog input selection (bits 2:0)? on page 34 ? outlines the bit settings necessary to control the input multiplexer and mic gain. ?channel b pga control - address 07h? on page 32 and ?channel a pga control - address 08h? on page 33 outline the register settings necessar y to control the pga. by default, line- level input 1 is selected, and the pga is set to 0 db. 5.5 input connections the analog modulator samples the i nput at 6.144 mhz (mclk=12.288 mhz). the digital filter will reject sig- nals within the stopband of the filter. however, th ere is no rejection for input signals which are (n ? 6.144 mhz) the digital passband frequency, where n=0,1,2,... refer to the typical connection diagram for the recommended analog input circ uit that will attenuate no ise energy at 6.144 m hz. the use of capac- itors which have a large voltage coe fficient (such as general-purpose ceramics) must be avoided since these can degrade signal linearity. any unused analog input pairs should be left unconnected. 5.5.1 analog input configuration for 1 v rms input levels the cs5346 pga, excluding the input multiplexer, is shown in figure 10 with nominal component values. interfacing to this circuit is a rela tively simple matter and several opti ons are available. the simplest option is shown in figure 11. however, it may be advantageo us in some applications to provide a low-pass filter prior to the pga to prevent radio frequency interference within the amplifier. the circuit shown in figure 12 mux +32 db ain1a ain2a ain3a ain4a/micin1 ain5a ain6a pga mux +32 db ain1b ain2b ain3b ain4b/micin2 ain5b ain6b analog input selection bits channel a pga gain bits channel b pga gain bits out to adc channel a out to adc channel b pga figure 9. analog input architecture
24 ds861pp2 cs5346 demonstrates a simple solution. the 1800 pf capacitors in the low-pass filter should be c0g or equivalent to avoid distortion issues . 5.5.2 analog input c onfiguration for 2 v rms input levels the cs5346 can also be easily configured to support an external 2 v rms input signal, as shown in figure 13. in this configuration, the 2 v rms input signal is attenuated to 1.5 v rms at the analog input with the external 12 k ? resistor and the input impedance to the network is increased to 48 k ? . the pga gain must also be configured to attenuate the 1.5 v rms at the input pin to the 1.0 v rms maximum a/d input level to prevent clipping in the adc. 36 k v cm 9 k to 144 k a/ d input - + ? ? ? analog input cs5346 figure 10. cs5346 pga 36 k v cm 9 k to 144 k a/ d input - + ? ? ? 2. 2 f 100 k ? analog input cs5346 figure 11. 1 v rms input circuit 36 k v cm 9 k to 144 k a/d input 2.2 f 1800 pf 100 k ? 100 ? - + analog input figure 12. 1 v rms input circuit with rf filtering 36 k v cm 9 k to 144 k a/ d input - + 2. 2 f 18 pf 100 k ? 12 k ? analog input ? ? ? cs5346 figure 13. 2 v rms input circuit
ds861pp2 25 cs5346 5.6 pga auxiliary analog output the cs5346 includes an auxiliary an alog output thro ugh the pgaout pins. thes e pins can be configured to output the analog input to the adc as selected by the input mux and gained or attenuated with the pga, or alternatively, they may be set to high impedance. see the ?pgaout source select (bit 6)? on page 32 for information on configuring t he pga auxiliary analog output. the pga auxiliary analog output can so urce very little current. as curren t from the pgaout pins increases, distortion will increase. for this reason, a high-input impedance buffer must be used on the pgaout pins to achieve full performance. an example buffer for pgaout is prov ided on the cdb5346 for reference. re- fer to the table in ?dc electrical characteristics? on page 14 for acceptable loading conditions. 5.7 control port description and timing the control port is used to access the registers, allo wing the cs5346 to be configured for the desired oper- ational modes and formats. the operation of the contro l port may be completely asynchronous with respect to the audio sample rates. however, to avoid potential interference problems, the control port pins should remain static if no operation is required. the control port has two modes: spi and i2c, with th e cs5346 acting as a slave device. spi mode is se- lected if there is a high-to-low transition on the ad0/cs pin, after the rst pin has been brought high. i2c mode is selected by connecting the ad0/cs pin through a resistor to vlc or dgnd, thereby permanently selecting the desired ad0 bit address state. 5.7.1 spi mode in spi mode, cs is the chip-select signal; cclk is the contro l port bit clock (input into the cs5346 from the microcontroller); cdin is the in put data line from the microcontrolle r; cdout is the output data line to the microcontroller. data is clocked in on the rising edge of cclk and out on the falling edge. figure 14 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first seven bits on cdin form the chip address and mu st be 1001111. the eighth bit is a read/write indi- cator (r/w ), which should be low to write. the next eigh t bits form the memory address pointer (map), which is set to the address of the regi ster that is to be updated. the ne xt eight bits are the data that will be placed into the register designated by the map. during writes, the cdout output stays in the hi-z state. it may be externally pulled high or low with a 47 k ? resistor, if desired. to read a register, the map has to be set to the correct address by ex ecuting a partial write cycle which finishes (cs high) immediately after the map byte. to begin a read, bring cs low, send out the chip ad-
26 ds861pp2 cs5346 dress and set the read/write bit (r/w ) high. the next falling edge of cc lk will clock out the msb of the addressed register (cdout will le ave the high-im pedance state). for both read and write cycles, th e memory address pointer will auto matically increment following each data byte in order to fac ilitate block reads an d writes of successive registers. 5.7.2 i2c mode in i2c mode, sda is a bidirectional da ta line. data is clocked into and ou t of the part by the clock, scl. there is no cs pin. pins ad0 and ad1 form the two least-sign ificant bits of the ch ip address and should be connected through a resistor to vlc or dgnd as de sired. the state of the pins is sensed while the cs5346 is being reset. the signal timings for a read and write cycle are shown in figure 15 and figure 16 . a start condition is defined as a falling transition of sda while the clock is high. a stop condition is a rising transition while the clock is high. all other transition s of sda occur while the clock is low. the first byte sent to the cs5346 after a start condition consists of a 7-bit chip address field and a r/w bit (high for a read, low for a write). the upper 5 bits of the 7-bit address field are fix ed at 10011. to communicate with a cs5346, the chip address field, which is the first byte sent to the cs5346, should match 10011 followed by the settings of the ad1 and ad0. the 8th bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address pointer (map) which selects the register to be read or written. if the operation is a read, the contents of the register pointed to by the map will be output. following each data byte, the memory address pointer will automatically incr ement to facilitate block reads and writes of successive registers. each byte is separated by an acknowledge bit. the ack bit is output from the cs5346 after each input byte is read, and is input to the cs5346 from the microcontro ller after each transmitted byte. map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 0010000 figure 14. control port timing in spi mode 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 ad1 ad0 0 sda 6 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n figure 15. control port timing, i2c write
ds861pp2 27 cs5346 since the read operation cannot set the map, an aborted write operation is used as a preamble. as shown in figure 16 , the write operation is aborted after the ackno wledge for the map byte by sending a stop con- dition. the following pseudocode illu strates an aborted wr ite operation followed by a read operation. ? send start condition. ? send 10011xx0 (chip address & write operation). ? receive acknowledge bit. ? send map byte. ? receive acknowledge bit. ? send stop condition, aborting write. ? send start condition. ? send 10011xx1(chip address & read operation). ? receive acknowledge bit. ? receive byte, contents of selected register. ? send acknowledge bit. ? send stop condition. 5.8 interrupts and overflow the cs5346 has a comprehens ive interrupt capabilit y. the int output pin is int ended to drive the interrupt input pin on the host microcontroller. the int pin may function as either an active high cmos driver or an active-low, open-drain driver (see ?active high/lo w (bit 0)? on page 35). when configured as active low open-drain, the int pin has no active pull-up transistor, allowing it to be used for wired-or hook-ups with multiple peripherals connected to the microcontrolle r interrupt input pin. in this configuration, an ex- ternal pull-up resistor must be placed on the int pin for proper operation. many conditions can cause an interrupt, as listed in the interrupt status register descriptions (see ?inter- rupt status - address 0dh? on page 35). each sour ce may be masked off through mask register bits. in addition, each source may be set to rising edge, falling edge, or level-sensitive. combined with the option of level-sensitive or edge-sensitive modes within the microcontroller, many different configurations are possible, depending on the needs of the equipment designer. the cs5346 also has a dedicated overflow output. t he ovfl pin functions as active low open drain and has no active pull-up transistor, thereby requiring an external pull-up resistor. the ovfl pin outputs an or of the adcoverflow and adcunderf low conditions available in the in terrupt status register; however, these conditions do not need to be unmask ed for proper operation of the ovfl pin. scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 ad1 ad0 0 sda 1 0 0 1 1 ad1 ad0 1 chip address (read) start 7 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop figure 16. control port timing, i2c read
28 ds861pp2 cs5346 5.9 reset when rst is low, the cs5346 enters a low-power mode and all internal states are reset, including the con- trol port and registers, the outputs are muted. when rst is high, the control port becomes operational, and the desired settings should be loaded into the control registers. writing a 0 to the pdn bit in the power con- trol register will then cause the part to l eave the low-power stat e and begin operation. the delta-sigma modulators settle in a matter of mi croseconds after the analog section is powered, either through the application of power or by setting the rst pin high. however, the voltage reference will take much longer to reach a final value due to the presence of external capacitance on the filt+ pin. during this voltage referenc e ramp delay, sdout will be automatically muted. it is recommended that rst be activated if the analog or digital supplies drop below the recommended op- erating condition to prevent power-glitch-related issues. 5.10 synchronization of multiple devices in systems where multiple adcs are required, care must be taken to achieve simultaneous sampling. to ensure synchronou s sampling, the master clocks and left/righ t clocks must be the same for all of the cs5346s in the system. if only one master clock source is needed, one solution is to place one cs5346 in master mode, and slave all of the other cs5346s to th e one master. if multiple master clock sources are needed, a possible solution would be to supply all cl ocks from the same external source and time the cs5346 reset with the inactive edge of master clock. this will ensure that all conv erters begin sampling on the same clock edge. 5.11 grounding and power supply decoupling as with any high-resolution converter, the cs5346 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. figure 7 shows the recommended power ar- rangements, with va connected to a clean supply. vd, which powers the digital filter, may be run from the system logic supplies (vls or vlc). power supply decoupling capacitors should be as near to the cs5346 as possible, with the low value ceramic capacitor being the nearest. all signals, especially clocks, should be kept away from the filt+ and vq pins in order to avoid unwanted coupling into the modulators. the filt+ and vq decoupling capacitors, partic ularly the 0.1 f, must be positione d to minimize the electrical path from filt+ and agnd. the cs5346 evaluation board demonstrates the optimum layout and power supply arrangements. to minimize digital noise, connect the cs5346 digital outputs only to cmos inputs.
ds861pp2 29 cs5346 6. register qu ick reference this table shows the register names and their associat ed default values. addr function 7 6 5 4 3 2 1 0 01h chip id part3 part2 part1 part0 rev3 rev2 rev1 rev0 pg. 30 1100 x x x x 02h power control freeze reserved reserved reserved pdn_mic pdn_adc reserved pdn pg. 30 0000 0 0 0 1 03h reserved reserved reserved reserved reserved reserved reserved reserved reserved 0000 1 0 0 0 04h adc control fm1 fm0 reserved dif reserved mute hpffreeze m/s pg. 31 0000 0 0 0 0 05h mclk frequency reserved mclk freq2 mclk freq1 mclk freq0 reserved reserved reserved reserved pg. 32 0000 0 0 0 0 06h pgaout control reserved pgaout reserved reserved re served reserved reserved reserved pg. 32 0100 0 0 0 0 07h pga ch b gain control reserved reserved gain5 gain4 gain3 gain2 gain1 gain0 pg. 32 0000 0 0 0 0 08h pga ch a gain control reserved reserved gain5 gain4 gain3 gain2 gain1 gain0 pg. 33 0000 0 0 0 0 09h analog input control reserved reserved reserved pgasoft pgazero sel2 sel1 sel0 pg. 33 0001 1 0 0 1 0ah - 0bh reserved reserved reserved reserved rese rved reserved reserved reserved reserved 0000 0 0 0 0 0ch active level control reserved reserved reserved reserved reserved reserved reserved active_h/l pg. 34 1100 0 0 0 0 0dh interrupt status reserved reserved re served reserved clkerr reserved ovfl undrfl pg. 34 0000 0 0 0 0 0eh interrupt mask reserved reserved rese rved reserved clkerrm reserved ovflm undrflm pg. 35 0000 0 0 0 0 0fh interrupt mode msb reserved reserved reserved reserved clkerr1 reserved ovfl1 undrfl1 pg. 35 0000 0 0 0 0 10h interrupt mode lsb reserved reserved reserved reserved clkerr0 reserved ovfl0 undrfl0 pg. 35 0000 0 0 0 0
30 ds861pp2 cs5346 7. register description 7.1 chip id - register 01h function: this register is read-only. bits 7 through 4 are the part number id, which is 1100b, and the remaining bits (3 through 0) indicate the device revision as shown in table 4 below. 7.2 power control - address 02h 7.2.1 freeze (bit 7) function: this function allows modifications to be made to certai n control port bits without the changes taking effect until the freeze bit is disabled. to make multiple changes to these bits take effect simultaneously, set the freeze bit, make all changes, then clear the freeze bit. the bits affected by the fr eeze function are listed in table 5 . 7.2.2 power-down mic (bit 3) function: the microphone preamp lifier block will enter a low-power state whenever this bit is set. 7.2.3 power-down adc (bit 2) function: the adc pair will remain in a reset state whenever this bit is set. 7.2.4 power-down device (bit 0) function: the device will enter a low-power state whenever this bit is set. the powe r-down bit is set by default and must be cleared before normal operation can occur. the contents of the control registers are retained when the device is in power-down. 76543210 part3 part2 part1 part0 rev3 rev2 rev1 rev0 rev[3:0] revision 0000 a1 table 4. device revision 76543210 freeze reserved reserved reserved pdn_mic pdn_adc reserved pdn name register bit(s) mute 04h 2 gain[5:0] 07h 5:0 gain[5:0] 08h 5:0 table 5. freeze-able bits
ds861pp2 31 cs5346 7.3 adc control - address 04h 7.3.1 functional mode (bits 7:6) function: selects the required range of sample rates. 7.3.2 digital interface format (bit 4) function: the required relationship between lrck, sclk and sdout is defined by the digital interface format bit. the options are detailed in table 7 and may be seen in figure 3 and figure 4 . 7.3.3 mute (bit 2) function: when this bit is set, the serial audio output of the both channels is muted. 7.3.4 high-pass filt er freeze (bit 1) function: when this bit is set, the internal high-pass filter is disa bled.the current dc offset value will be frozen and continue to be subtracted from the conversion result. see ?high-pass filter and dc offset calibration? on page 22. 7.3.5 master / slave mode (bit 0) function: this bit selects either master or slave operation for the serial audio port. setting this bit selects master mode, while clearing this bit selects slave mode. 76543210 fm1 fm0 reserved dif reserved mute hpffreeze m/s fm1 fm0 mode 0 0 single-speed mode: 8 to 50 khz sample rates 0 1 double-speed mode: 50 to 100 khz sample rates 1 0 quad-speed mode: 100 to 200 khz sample rates 11reserved table 6. functional mode selection dif description format figure 0 left-justified (default) 0 3 1i2s 1 4 table 7. digital interface formats
32 ds861pp2 cs5346 7.4 mclk frequency - address 05h 7.4.1 master clock di viders (bits 6:4) function: sets the frequency of the supplied mclk signal. see table 8 for the appropriate settings. 7.5 pgaout control - address 06h 7.5.1 pgaout source select (bit 6) function: this bit is used to configure the pgaout pins to be either high impedance or pga outputs. refer to table 9 . 7.6 channel b pga control - address 07h 7.6.1 channel b pga gain (bits 5:0) function: see ?channel a pga gain (bits 5:0)? on page 33. 76543210 reserved mclk freq2 mclk freq1 mclk freq0 reserved reserved reserved reserved mclk divider mclk freq2 mclk freq1 mclk freq0 1 000 1.5 001 2 010 3 011 4 100 reserved 101 reserved 11x table 8. mclk frequency 76543210 reserved pgaout reserved reserved reserved reserved reserved reserved pgaout pgaouta & pgaoutb 0 high impedance 1 pga output table 9. pgaout source selection 76543210 reserved reserved gain5 gain4 gain3 gain2 gain1 gain0
ds861pp2 33 cs5346 7.7 channel a pga c ontrol - a ddress 08h 7.7.1 channel a pga gain (bits 5:0) function: sets the gain or attenuation for the adc input pg a stage. the gain may be adjusted from -12 db to +12 db in 0.5 db steps. the gain bits are in two?s complement with the gain0 bit set for a 0.5 db step. register settings outside of the 12 db ran ge are reserved and must not be used. see table 10 for ex- ample settings. 7.8 adc input cont rol - address 09h 7.8.1 pga soft ramp or ze ro cross enable (bits 4:3) function: soft ramp enable soft ramp allows level changes, both muting and a ttenuation, to be implemented by incrementally ramp- ing, in 1/8 db steps, from the current level to the ne w level at a rate of 1 db per 8 left/right clock periods. see table 11 . zero cross enable zero cross enable dictates that sign al-level changes, either by attenu ation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. the requested level change will occur after a time- out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. see table 11 . soft ramp and zero cross enable soft ramp and zero cross enable dictate that signa l-level changes, either by attenuation changes or mut- ing, will occur in 1/8 db steps a nd be implemented on a sig nal zero crossing. the 1/8 db level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sam- ple rate) if the signal does not encounter a zero cros sing. the zero cross function is independently mon- itored and implemented for each channel. see table 11 . 76543210 reserved reserved gain5 gain4 gain3 gain2 gain1 gain0 gain[5:0] setting 101000 -12 db 000000 0 db 011000 +12 db table 10. example gain and attenuation settings 76543210 reserved reserved reserved pg asoft pgazero sel2 sel1 sel0
34 ds861pp2 cs5346 7.8.2 analog input se lection (bits 2:0) function: these bits are used to select the input source for the pga and adc. please see table 12 . 7.9 active level cont rol - address 0ch 7.9.1 active high/ low (bit 0) function: when this bit is set, the int pin functions as an active high cmos driver. when this bit is cleared, the int pin functions as an active low open drain driver and will require an exter- nal pull-up resistor for proper operation. 7.10 status - address 0dh for all bits in this register, a ?1? means the associated condition has occurred at l east once since the register was last read. a ?0? means the associated condition has not occurred since the last reading of the register. status bits that are masked off in th e associated mask register will always be ?0? in this regi ster. this register defaults to 00h. pgasoft pgazerocross mode 0 0 changes to affect immediately 0 1 zero cross enabled 1 0 soft ramp enabled 1 1 soft ramp and zero cross enabled (default) table 11. pga soft cross or zero cross mode selection sel2 sel1 sel0 pga/adc input 0 0 0 microphone-level inputs (+32 db gain enabled) 0 0 1 line-level input pair 1 0 1 0 line-level input pair 2 0 1 1 line-level input pair 3 1 0 0 line-level input pair 4 1 0 1 line-level input pair 5 1 1 0 line-level input pair 6 1 1 1 reserved table 12. analog input multiplexer selection 76543210 reserved reserved reserved reserved re served reserved reserved active_h/l 76543210 reserved reserved reserved rese rved clkerr reserved ovfl undrfl
ds861pp2 35 cs5346 7.10.1 clock error (bit 3) function: indicates the occurrence of a clock error condition. 7.10.2 overflow (bit 1) function: indicates the occurrence of an adc overflow condition. 7.10.3 underflow (bit 0) function: indicates the occurrence of an adc underflow condition. 7.11 status mask - address 0eh function: the bits of this register serve as a mask for the status sources found in the register ?status - address 0dh? on page 34 . if a mask bit is set to 1, the error is unmask ed, meaning that its occu rrence will affect the status register. if a mask bit is set to 0, the error is masked, mean ing that its occurrence will not affect the status register. the bit positions align with the corresponding bits in the status register. 7.12 status mode msb - address 0fh 7.13 status mode lsb - address 10h function: the two status mode registers form a 2-bit code for ea ch status register function. there are three ways to update the status register in accordance with the status condition. in the rising -edge active mode, the sta- tus bit becomes active on the arrival of the conditio n. in the falling-edge active mode, the status bit be- comes active on the removal of the condition. in leve l-active mode, the status bit is active during the condition. 00 - rising edge active 01 - falling edge active 10 - level active 11 - reserved 76543210 reserved reserved reserved reserv ed clkerrm reserved ovflm undrflm 76543210 reserved reserved reserved reserved clkerr1 reserved ovfl1 undrfl1 reserved reserved reserved reserved clkerr0 reserved ovfl0 undrfl0
36 ds861pp2 cs5346 8. parameter definitions dynamic range the ratio of the rms value of the signal to the rms su m of all other spectral co mponents over the specified bandwidth. dynamic range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is added to resulting measur ement to refer the measur ement to full scale. this technique ensures that the distortion components are below the noise level and do not affect the measure- ment. this measurement te chnique has been accepted by the au dio engineering society, aes17-1991, and the electronic industries as sociation of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms su m of all other spectral co mponents over the specified bandwidth (typically 10 hz to 20 khz), including di stortion components. expre ssed in decibels. measured at -1 and -20 dbfs as sug gested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right ch annels. measured for each c hannel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. units in deci- bels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain drift the change in gain value with temperature. units in ppm/c.
ds861pp2 37 cs5346 9. filter plots figure 17. single-speed stopband rejection f igure 18. single-speed stopband rejection figure 19. single-speed transition band (detail) figure 20. single-speed passband ripple figure 21. double-speed stopband rejection figure 22. double-speed stopband rejection -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0 0 .05 0 .1 0 .15 0.2 0 .25 0.3 0 .35 0.4 0 .45 0 .5 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db)
38 ds861pp2 cs5346 figure 23. double-speed transition band (detail) figure 24. double-speed passband ripple figure 25. quad-speed stopband rejection figure 26. quad-speed stopband rejection figure 27. quad-speed transition band (d etail) figure 28. quad-speed passband ripple -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.46 0.47 0.48 0.49 0.50 0.51 0.52 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 frequency (normalized to fs) amplitude (db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28 frequency (normalized to fs) amplitude (db)
ds861pp2 39 cs5346 10.package dimensions 11.thermal characteristics and specifications 1. ? ja is specified according to jedec sp ecifications for multi-layer pcbs. inches millimeters dim min nom max min nom max a --- 0.055 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.009 0.011 0.17 0.22 0.27 d 0.343 0.354 0.366 8.70 9.0 bsc 9.30 d1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e 0.343 0.354 0.366 8.70 9.0 bsc 9.30 e1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e* 0.016 0.020 0.024 0.40 0.50 bsc 0.60 l 0.018 0.24 0.030 0.45 0.60 0.75 ? 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mm *controlling dimension is mm. *jedec designation: ms022 parameters symbol min typ max units package thermal resistance (note 1) 48-lqfp ? ja ? jc - - 48 15 - - c/watt c/watt allowable junction temperature --125 ? c 48l lqfp package drawing e1 e d1 d 1 e l ? b a1 a
40 ds861pp2 cs5346 12.ordering information 13.revision history product description package pb-free grade temp range container order # cs5346 24-bit, 192 khz stereo audio adc 48-lqfp yes commercial -40 to +85 c tray cs5346-cqz tape & reel CS5346-CQZR cs5346 24-bit, 192 khz stereo audio adc 48-lqfp yes automotive -40 to +105 c tray cs5346-dqz tape & reel cs5346-dqzr cdb5346 cs5346 evaluation board no - - - cdb5346 release changes a1 advance release pp1 -updated title -added text to section 2. on page 7 -added v/v representations for pga and mic gain specifications -updated automotive thd+n and dnr limits -added reference to cdb5346 in section 5.6 on page 25 pp2 -added note 3 and note for afilta/afiltb capacitors in figure 7 . contacting cirrus logic support for all product questions and inquiries, c ontact a cirrus logic sales representative. to find the one nearest you, go to www.cirrus.com important notice ?preliminary? product information describes products that are in production, but for which full characterization data is not ye t available. cirrus logic, inc. and its sub- sidiaries (?cirrus?) believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to obtain the latest version of re levant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and condit ions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnif ication, and limitation of liability. no responsibility is assu med by cirrus for the use of this informa- tion, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or ot her rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, m ask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herei n and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of c irrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resal e. certain applications usin g semiconductor products may involve potential ri sks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not designed, authorized or warranted for use in products surgically implanted into the body, automotive safety or security devices, life su pport products or other crit- ical applications. inclusio n of cirrus products in such applications is under stood to be fully at the customer's risk and cir- rus disclaims and makes no warranty, express, statutory or im plied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in su ch a manner. if the customer or custom- er's customer uses or permits th e use of cirrus products in cri tical applications, cu stomer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including at- torneys' fees and costs, that may result fr om or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. i2c is a registered trademark of philips semiconductor. spi is a trademark of motorola, inc.

▲Up To Search▲

Price & Availability of CS5346-CQZR

	To Download CS5346-CQZR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .